The electronics industry continues to rely upon advances in semiconductor technology to realize higher-function devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor (MOS) transistors, such as p-channel MOS (PMOS), n-channel MOS (NMOS) and complementary MOS (CMOS) transistors, bipolar transistors, and BiCMOS transistors.
Each of these semiconductor devices generally includes a semiconductor substrate on which a number of active devices are formed. The particular structure of a given active device can vary between device types. For example, in MOS transistors, an active device generally includes source and drain regions and a gate electrode that modulates current between the source and drain regions.
One important step in the manufacturing of such devices is the formation of devices, or portions thereof, using photolithography and etching processes. In photolithography, a wafer substrate is coated with a light-sensitive material called photo-resist. Next, the wafer is exposed to light; the light striking the wafer is passed through a mask plate. This mask plate defines those desired features on which areas of the substrate will be printed. After exposure, the resist-coated wafer substrate is developed. The desired features as defined on the mask are retained on the photo resist-coated substrate. Unexposed areas of resist are washed away with a developer. The wafer having the desired features defined is subjected to etching. Depending upon the production process, the etching may either be a wet etch, in which liquid chemicals are used to remove wafer material or a dry etch, in which wafer material is subjected to a radio frequency (RF) induced plasma.
Often desired features have particular regions in which the final printed and etched regions have to be accurately reproduced over time. These regions are characterized by critical dimensions (CDs). As device geometry approaches the sub-micron realm, wafer fabrication becomes more reliant on maintaining consistent CDs over normal process variations. The active device dimensions as designed and replicated on the photo mask and those actually rendered on the wafer substrate have to be repeatable and controllable. In many situations, the process attempts to maintain the final CDs equal to the masking CDs. However, imperfections in the process or changes in technology (that may be realized in a given fabrication process, if the process were “tweaked”) often necessitate the rendering of final CDs that deviate from the masking CDs.
U.S. Pat. No. 5,757,507 of Ausschnitt et al. relates generally to manufacturing processes requiring lithography and, more particularly, to monitoring of bias and overlay error in lithographic and etch processes used in microelectronics manufacturing which is particularly useful in monitoring pattern features with dimensions on the order of less than 0.5 micron.
U.S. Pat. No. 5,962,173 of Leroux et al. relates generally to the field of fabricating integrated circuits and more particularly to maintaining accuracy in the fabrication of such circuits having extremely narrow line elements such as gate lines.
U.S. Pat. No. 5,902,703 of Leroux et al. relates generally to the field of fabricating integrated circuits and more particularly to maintaining accuracy in the fabrication of such circuits having relatively narrow line elements such as gate lines. The invention is also directed to the verification of stepper lens fabrication quality.
U.S. Pat. No. 5,976,741 of Ziger et al. relates generally to methods of determining illumination exposure dosages and other processing parameters in the field of fabricating integrated circuits. More particularly, the invention concerns methods of processing semiconductor wafers in step and repeat systems.
U.S. Pat. No. 6,301,008 B1 of Ziger et al. relates to semiconductor devices and their manufacture, and more particularly, to arrangements and processes for developing relatively narrow line widths of elements such as gate lines, while maintaining accuracy in their fabrication.
U.S. patent application U.S. 2002/0182516 A1 of Bowes relates generally to metrology of semiconductor manufacturing processes. More particularly, the present invention is a needle comb reticle pattern for simultaneously making critical dimension (CD) measurements of device features and registration measurements of mask overlays relative to semiconductor wafers during processing of semiconductor wafers. This reference and those previously cited are herein incorporated by reference in their entirety.
In gauging the quality of the printing of the CDs in a wafer process, a Scanning Electron Microscope (SEM) is used to measure the lines and space that define CDs. However, the use of a SEM reduces the throughput time in the wafer fabrication